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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
BASIC mSDRAM
1
EM_SDCLK
EM_CS[1:0]
EM_DQM[1:0]
EM_BA[1:0]
READ OPERATION
3
5
7
7
2
3
7
7
2
5
EM_A[20:0]
19
17
20
2 EM_CLK Delay
17
EM_D[15:0]
EM_SDRAS
11
11
13
13
EM_SDCAS
EM_WE
Figure 5-17. EMIF Basic SDRAM/mSDRAM Read Operation
3
1
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
4
8
6
5
9
7
10
EM_OE
13
12
EM_D[15:0]
EM_WE
Figure 5-18. Asynchronous Memory Read Timing for EMIF
100
Peripheral Information and Electrical Specifications
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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